core
core contains the basic functionality of pyripherals.
Register for internal registers,
Endpoint for Opal Kelly Endpoints on the FPGA, and
FPGA for basic FPGA connection and commands.
Module to configure OpalKelly XEM7310 FPGA to communicate with peripherals.
Use Registers for peripherals’ internal registers and Endpoints for Opal Kelly Endpoints on the FPGA.
Abe Stroschein, ajstroschein@stthomas.edu
Lucas Koerner, koer2434@stthomas.edu
- class pyripherals.core.Endpoint(address, bit_index_low, bit_width, gen_bit, gen_address, addr_step=1)[source]
Class for Opal Kelly endpoints on the FPGA.
- endpoints_from_defines
Class attribute. Dictionary of each group of endpoints paired with inner dictionaries of endpoint names to Endpoint objects, starts empty.
- Type
dict
- I2CDAQ_level_shifted
Class attribute. Dictionary of Endpoints for the level shifted I2CDAQ bus.
- Type
dict
- I2CDAQ_QW
Class attribute. Dictionary of Endpoints for QW 3.3V I2CDAQ bus.
- Type
dict
- address
Address location of the Endpoint.
- Type
int
- bit_index_low
Index of the LSB of the Endpoint.
- Type
int
- bit_index_high
Index of the MSB of the Endpoint.
- Type
int
- bit_width
Width of the Endpoint in bits. This number is used when using advance_endpoints if gen_bit is True.
- Type
int
- gen_bit
Whether to increment the bits when incrementing the Endpoint.
- Type
bool
- gen_address
Whether to increment the address when incrementing the Endpoint.
- Type
bool
- addr_step
How much to add to the address when using advance_endpoints if gen_address is True.
- Type
int
- static advance_endpoints(endpoints_dict, advance_num=1)[source]
Advances Endpoints in a dict in place by advance_num.
Checks each Endpoint’s gen_bit and gen_address attributes to see whether to increment the bit or the address or both. The Endpoint’s bit_width and addr_step attributes determine how much to increment the bits or address by. If the Endpoint’s bits would exceed Endpoint.MAX_WIDTH (determined from config.yaml), then the bits wrap around to start at bit zero on the next address determined by adding the Endpoint’s addr_step attribute.
- Example usage:
endpoints=Endpoint.advance_endpoints(Endpoint.get_chip_endpoints(‘I2CDAQ’),1)
- Parameters
endpoints_dict (dict of Endpoints) – The dict of Endpoints to advance by advance_num.
advance_num (int) – How much to advance the Endpoints by.
- Returns
dict
- Return type
the same dict of Endpoints given in endpoints_dict, now advanced
- static excel_to_defines(excel_path, defines_path, sheet=0)[source]
Convert an Excel spreadsheet of endpoint definitions to Verilog.
- Parameters
excel_path (str) – The path to the Excel spreadsheet to convert.
defines_path (str) – The path to the Verilog file to create.
sheet (int or str) – Optional. The int index of the sheet to read from the Excel spreadsheet, or the str sheet name.
- Returns
str
- Return type
the text written to the Verilog file.
- class pyripherals.core.FPGA(bitfile='default', endpoints=None, debug=False)[source]
Class for the Opal Kelly FPGA itself. Derived from OpalKelly Python examples.
- bitfile
Path to the bitfile to load on the FPGA.
- Type
str
- xem
Opal Kelly API connection to the FPGA.
- Type
ok.okCFrontPanel
- device_info
General information about the FPGA.
- Type
ok.okTDeviceInfo
- init_device()[source]
Initialize the FPGA for use and print device information.
Connect to the FPGA and load the bitfile. Return False on any errors. Only run this once or the FPGA connection will fail.
- read_pipe_out(addr, data_len=1024)[source]
Return the filled buffer and error code after reading an OK PipeOut. data_len is length in bytes (must be multiple of 16) returns: bytearray; error code
- read_trig(ep_bit)[source]
Read an OK TriggerOut Endpoint.
- Parameters
ep_bit (Endpoint) – The endpoint containing the bit_index_low and address of the TriggerOut to read.
- Returns
Whether the TriggerOut has been triggered.
- Return type
bool
- send_trig(ep_bit)[source]
Return the error code after activating an OK TriggerIn Endpoint.
Expects a single bit, not yet implement for multiple bits and will only activate the LSB if the Endpoint containts multiple bits.
- set_ep_simultaneous(address, bit_list, val_list)[source]
set multiple values to the wire of a single endpoint
- class pyripherals.core.Register(address, default, bit_index_high, bit_index_low, bit_width)[source]
Class for internal registers on a device.
- address
Address location of the register.
- Type
int
- default
Default value of the register.
- Type
int
- bit_index_high
Index of the MSB in the register.
- Type
int
- bit_index_low
Index of the LSB in the register.
- Type
int
- bit_width
Width of the register in bits.
- Type
int
- pyripherals.core.disp_device(dev, reg=True)[source]
Display endpoints and registers for a chip.
- Parameters
dev (I2CController or SPIController or SPIFifoDriven or AD7961) – Chip instance to display information for.
reg (bool) – Whether to display registers.